Internal Oscillation Clock Operation Mode; Setting And Operation Status; Releasing Internal Oscillation Clock Operation Mode - NEC V850ES/KE1+ User Manual

32-bit single-chip microcontrollers
Table of Contents

Advertisement

21.4 Internal Oscillation Clock Operation Mode

21.4.1 Setting and operation status

<R>
If watchdog timer 2 overflows during the oscillation stabilization time securing period after a reset is released or
after the STOP mode is released (overflow of the counter by setting the OSTS register), the internal oscillation clock
operation mode is set.
For details, refer to Figure 19-1 Status Transition.
A stop (error) of the main clock oscillation (f
• During normal operation: When the main clock is monitored by the internal oscillation clock (clock monitor)
• During oscillation stabilization time securing period: When WDT2 overflow occurs
Table 21-3 shows the operation status in the internal oscillation clock operation mode.
Counter overflow time by
OSTS register setting
Watchdog timer 2 overflow
time
Note The oscillation stabilization time can be changed by setting the mask option/option byte. For details, refer to
CHAPTER 25 MASK OPTION/OPTION BYTE.
Cautions 1. Set so as to make the watchdog timer 2 overflow time longer than the oscillation stabilization
time (OSTS register setting).
oscillation stabilization time (OSTS register setting), the oscillation is incorrectly judged as
stopped, regardless of whether the main clock oscillation is correctly operating when the
STOP mode is released by an interrupt. The internal oscillation clock operation mode will
then be unintentionally set.
2. When the internal oscillation clock operation mode is set, do not rewrite the WDTM2 and
WDTE registers in 1,024 internal oscillation clocks (f

21.4.2 Releasing internal oscillation clock operation mode

<R>
The internal oscillation clock operation mode is released by reset (RESET input, WDT reset, etc.).
While securing the oscillation stabilization time after reset is released, if the OSTS register overflows before
watchdog timer 2 overflows, the main clock oscillation (f
set.
For details, refer to Figure 19-1 Status Transition.
608
CHAPTER 21 CLOCK MONITOR
) is detected when as shown below.
X
Table 21-2. Overflow Time of OSTS Register and Watchdog Timer 2
After reset release
After STOP mode release by interrupt
13
21
(OSTS = 2
/f
to 2
/f
)
X
X
19
After reset release (2
/f
R
After STOP mode release by interrupt
12
19
(WDTM2 = 2
/f
to 2
/f
R
R
User's Manual U16896EJ2V0UD
Overflow Time
Note
13
Option
: 2
/f
0.819 ms @ 10 MHz, 1.638 ms @ 5 MHz
X
Note
15
Option
: 2
/f
3.277 ms @ 10 MHz, 6.554 ms @ 5 MHz
X
0.819 ms @ 10 MHz, 1.638 ms @ 5 MHz (MIN.)
209.7 ms @ 10 MHz, 419.4 ms @ 5 MHz (MAX.)
)
1,092 ms to 4,369 ms
8.5 ms to 34.1 ms (MIN.)
)
1,092 ms to 4,369 ms (MAX.)
If the watchdog timer 2 overflow time is shorter than the
) after the CPU operation is started.
R
) is judged as stabilized and the normal operation mode is
X

Advertisement

Table of Contents
loading

This manual is also suitable for:

?pd70f3302?pd703302?pd70f3302y?pd703302y

Table of Contents