NEC V850ES/KE1+ User Manual page 205

CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
<1> Count operation start flow
Register initial setting
TP0CTL0 register
(TP0CKS0 to TP0CKS2 bits)
TP0CTL1 register,
TP0IOC1 register,
TP0OPT0 register
TP0CE bit = 1
<2> Overflow flag clear flow
Read TP0OPT0 register
(check overflow flag).
TP0OVF bit = 1
Execute instruction to clear
TP0OVF bit (CLR TP0OVF).
<3> Count operation stop flow
TP0CE bit = 0
START
Initial setting of these registers
is performed before setting the
TP0CE bit to 1.
The TP0CKS0 to TP0CKS2 bits can
be set at the same time when counting
has been started (TP0CE bit = 1).
NO
YES
Counter is initialized and
counting is stopped by
clearing TP0CE bit to 0.
STOP
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