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13.5.2 Trigger modes
The V850ES/KE1+ has the following three trigger modes that set the A/D conversion start timing. These trigger
modes are set by the ADS register.
• Software trigger mode
• External trigger mode (hardware trigger mode)
• Timer trigger mode (hardware trigger mode)
(1) Software trigger mode
This mode is used to start A/D conversion by setting the ADM.ADCS bit to 1 while the ADS.TRG bit is 0.
Conversion is repeatedly performed as long as the ADCS bit is not cleared to 0 after completion of A/D
conversion.
If the ADM, ADS, PFM, or PFT register is written during conversion in the high-speed mode (ADM.ADHS1,
<R>
ADM.ADHS0 bits = 01 or 10), A/D conversion is aborted and started again from the beginning. Writing the
ADM, ADS, PFM, and PFT registers is prohibited during conversion operation in the normal mode (ADHS1,
ADHS0 bits = 00).
(2) External trigger mode (hardware trigger mode)
Use this in the high-speed mode (ADHS1, ADHS0 bits = 10 or 01). Inputting valid edge is prohibited during
<R>
A/D conversion operation in the normal mode (ADHS1, ADHS0 bits = 00).
This is the status in which the TRG bit is set to 1 and ADS.ADTMD bit is cleared to 0. This mode is used to
start A/D conversion by detecting an external trigger (ADTRG) after the ADCS bit has been set to 1.
The A/D converter waits for the external trigger (ADTRG) after the ADCS bit is set to 1.
The valid edge of the signal input to the ADTRG pin is specified by using the ADS.EGA1 and ADS.EGA0 bits.
When the specified valid edge is detected, A/D conversion is started.
When A/D conversion is completed, the A/D converter waits for the external trigger (ADTRG) again.
If a valid edge is input to the ADTRG pin during A/D conversion in the high-speed mode (ADHS1, ADHS0 bits
= 01 or 10), A/D conversion is aborted and started again from the beginning.
If the ADM, ADS, PFM, or PFT register is written during conversion in the high-speed mode (ADHS1, ADHS0
bits = 01 or 10), A/D conversion is aborted and the A/D converter waits for an external trigger (ADTRG).
(3) Timer trigger mode (hardware trigger mode)
Use this in the high-speed mode (ADHS1, ADHS0 bits = 10 or 01). Inputting valid edge is prohibited during
<R>
A/D conversion operation in the normal mode (ADHS1, ADHS0 bits = 00).
This mode is used to start A/D conversion by detecting a timer trigger (INTTM010) after the ADCS bit has
been set to 1 with the TGR bit = 1 and ADTMD bit = 1.
The A/D converter waits for the timer trigger (INTTM010) after the ADCS bit is set to 1.
When the INTTM010 signal is generated, A/D conversion is started.
When A/D conversion is completed, the A/D converter waits for the timer trigger (INTTM010) again.
If the INTTM010 signal is generated during A/D conversion in the high-speed mode (ADHS1, ADHS0 bits = 01
or 10), A/D conversion is aborted and started again from the beginning.
If the ADM, ADS, PFM, or PFT register is written during conversion in the high-speed mode (ADHS1, ADHS0
bits = 01 or 10), A/D conversion is aborted and the A/D converter waits for a timer trigger (INTTM010).
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CHAPTER 13 A/D CONVERTER
User's Manual U16896EJ2V0UD
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