Watchdog Timer Mode Register 1 (Wdtm1) - NEC V850ES/KE1+ User Manual

CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION

17.3.8 Watchdog timer mode register 1 (WDTM1)

This register is a special register that can be written to only in a special sequence. To generate a maskable
interrupt (INTWDT1), clear the WDTM14 bit to 0.
This register can be read or written in 8-bit or 1-bit units (for details, refer to CHAPTER 11 WATCHDOG TIMER
FUNCTIONS).
After reset: 00H
WDTM1
WDTM14
Notes 1. Once the RUN1 bit has been set (1), it cannot be cleared (0) by software.
2. Once the WDTM14 and WDTM13 bits have been set (1), they cannot be cleared (0)
3. For non-maskable interrupt servicing due to a non-maskable interrupt request signal
552
R/W Address: FFFFF6C2H
< >
RUN1 0 0 WDTM14 WDTM13
RUN1 Watchdog timer operation mode selection
0 Stop count operation
1 Clear counter and start count operation
WDTM13 Watchdog timer operation mode selection
0 0
Interval timer mode
(Generate maskable interrupt INTWDTM1 when overflow occurs)
0 1
1 0 Watchdog timer mode 1
(Generate non-maskable interrupt INTWDT1 when overflow occurs)
1 1
Watchdog timer mode 2
(Start WDTRES2 reset operation when overflow occurs)
Therefore, once counting starts, it cannot be stopped except by reset.
by software. Reset is the only way to clear these bits.
(INTWDT1), refer to 17.10 Cautions.
User's Manual U16896EJ2V0UD
0 0
Note 1
Note 2
Note 3
0