NEC V850ES/KE1+ User Manual page 200

Figure 6-31. Register Setting in Free-Running Timer Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE
TP0CTL0
0/1 0
Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1.
(b) TMP0 control register 1 (TP0CTL1)
TP0EST
TP0CTL1
0 0
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0IOC0
0 0
200
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
0 0 0
TP0EEE
0/1 0 0
TP0OL1
0 0 0/1
User's Manual U16896EJ2V0UD
TP0CKS2 TP0CKS1 TP0CKS0
0/1 0/1 0/1
TP0MD2 TP0MD1 TP0MD0
1 0 1
TP0OE1 TP0OL0 TP0OE0
0/1 0/1 0/1
Note
Select count clock
0: Stop counting
1: Enable counting
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TP0CKS0 to TP0CKS2 bits
1: Count on external
event count input signal
0: Disable TOP00 pin output
1: Enable TOP00 pin output
Setting of output level with
operation of TOP00 pin disabled
0: Low level
1: High level
0: Disable TOP01 pin output
1: Enable TOP01 pin output
Setting of output level with
operation of TOP01 pin disabled
0: Low level
1: High level