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20.4.2 Reset operation by WDTRES1 signal
If a reset operation mode in which reset is effected when watchdog timer 1 overflows is set, the system is reset
when watchdog timer 1 overflows (when the WDTRES1 signal is generated), and each hardware unit is initialized to a
specific status.
After watchdog timer 1 has overflowed, the system is reset for a specific duration of time (f
automatically released from the reset status. After release of the reset status, the CPU starts program execution.
Note that, because the main clock oscillator continues operating even during the reset period, the oscillation
stabilization time is not secured.
The following table shows the status of each hardware unit during the period of reset that is effected by the
WDTRES1 signal and after release of the reset status.
Table 20-3. Hardware Status on Occurrence of WDTRES1 Signal
Item
Main clock oscillator (f
)
X
Subclock oscillator (f
)
XT
Internal oscillator (f
)
R
Peripheral clock (f
to f
/1024)
XX
XX
Internal system clock (f
)
CLK
CPU clock (f
)
CPU
Watchdog timer 1 clock (f
)
XW
Internal RAM
I/O lines (P00)
I/O lines (ports other than P00)
On-chip peripheral I/O registers
Watchdog timer 2
Other on-chip peripheral functions
Figure 20-5. Timing of Reset Operation by Watchdog Timer 1
f
X
f
CLK
WDTRES1 signal
(active low)
Internal system
reset signal
(active low)
CHAPTER 20 RESET FUNCTION
During Reset
Oscillation continues
Oscillation continues
Oscillation continues
Operation stops
Oscillation continues (initialized to f
Oscillation continues (initialized to f
Operation continues
Undefined if writing data to RAM (by CPU) and reset input conflict (data is damaged).
Otherwise value immediately before reset input is retained.
Low-level output
High impedance
Initialized to specified status
Operation stops
Operation stops
f
CLK
User's Manual U16896EJ2V0UD
CLK
After Reset
Operation starts
/8)
XX
/8)
XX
Operation starts (f
Operation can be started
Initialized to f
/8 operation
XX
: 12-clock width
: 12 clocks) and then
/8)
R
595
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