Configuration - NEC V850ES/KE1+ User Manual

5.2 Configuration

<R>
FRC bit
XT1
Subclock
oscillator
XT2
MCK MFRC
bit
bit
X1
Main clock
oscillator
X2
Main clock
oscillator
stop control
STOP mode
CLKOUT Port CM
Remark f : Main clock oscillation frequency
X
f : Main clock frequency
XX
f : Internal system clock frequency
CLK
f : Subclock frequency
XT
f : CPU clock frequency
CPU
f : Watch timer clock frequency
BRG
f : Watchdog timer 1 clock frequency
XW
f : Internal oscillation clock frequency
R
126
CHAPTER 5 CLOCK GENERATION FUNCTION
Figure 5-1. Clock Generator
f
XT
IDLE mode
PLLON bit
f
f
XX
X IDLE
PLL
control
SELPLL bit
IDLE mode
IDLE
control
User's Manual U16896EJ2V0UD
f = f /2 to f
Interval timer BRG
X
BRG
IDLE mode
IDLE
control
CK2 to CK0 bits CLS bit, CK3 bit
Prescaler 2
f /32
XX
f /16
XX
f /8
XX
f /4
XX
f /2
XX
f
XX
Prescaler 1
f
Internal R
1/8
oscillator
f Watch timer clock,
XT
watchdog timer 2 clock
INTBRG
12
/2
X
Watch timer clock
Main clock stop
detection
HALT mode
f
HALT
CPU
CPU clock
control
Internal
f
CLK
system clock
f to f /1024
XX XX
Peripheral clock
f
XW
Watchdog timer 1 clock
f /8
R
Watchdog timer 2 clock
f /2048
R
1/256
TMH1 clock