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(4) TMP0 I/O control register 1 (TP0IOC1)
The TP0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIP00,
TIP01 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
TP0IOC1
Cautions 1. Rewrite
142
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
R/W
Address: FFFFF5A3H
6
5
7
0
0
0
TP0IS3
TP0IS2
Capture trigger input signal (TIP01 pin) valid edge setting
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
TP0IS1
TP0IS0
Capture trigger input signal (TIP00 pin) valid edge setting
0
0
No edge detection (capture operation invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
the
TP0CTL0.TP0CE bit = 0. (The same value can be written
when the TP0CE bit = 1.)
performed, clear the TP0CE bit to 0 and then set the bits
again.
2. The TP0IS3 to TP0IS0 bits are valid only in the free-
running timer mode and the pulse width measurement
mode.
In all other modes, a capture operation is not
possible.
User's Manual U16896EJ2V0UD
4
3
2
0
TP0IS3
TP0IS2
TP0IS3
to
TP0IS0
bits
If rewriting was mistakenly
1
0
TP0IS1
TP0IS0
when
the
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