NEC V850ES/KE1+ User Manual page 179

CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
(d) Conflict between trigger detection and match with TP0CCR0 register
If the trigger is detected immediately after the INTTP0CC0 signal is generated, the 16-bit counter is
cleared to 0000H and continues counting up. Therefore, the active period of the TOP01 pin is extended by
time from generation of the INTTP0CC0 signal to trigger detection.
16-bit counter
External trigger input
(TIP00 pin input)
TP0CCR0 register
INTTP0CC0 signal
TOP01 pin output
If the trigger is detected immediately before the INTTP0CC0 signal is generated, the INTTP0CC0 signal is
not generated. The 16-bit counter is cleared to 0000H, the TOP01 pin is asserted, and the counter
continues counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
External trigger input
(TIP00 pin input)
TP0CCR0 register
INTTP0CC0 signal
TOP01 pin output
− 1
FFFF 0000 D
0
D
0
− 1
FFFF 0000 D
0
D
0
User's Manual U16896EJ2V0UD
D 0000 0000
0
Extended
D 0000 0001
0
Shortened
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