Reset Operation By Wdtres2 Signal - NEC V850ES/KE1+ User Manual

20.4.3 Reset operation by WDTRES2 signal

If a reset operation mode in which reset is effected when watchdog timer 2 overflows is set, the system is reset
when watchdog timer 2 overflows (when the WDTRES2 signal is generated), and each hardware unit is initialized to a
specific status.
After watchdog timer 2 has overflowed, the system is reset for a specific duration of time (equivalent to analog
delay) and then automatically released from the reset status.
stabilization time of the main clock oscillator is secured, and then the CPU starts program execution.
Note that, because the main clock oscillator stops during the reset period, the oscillation stabilization time must be
secured. The oscillation stabilization time is determined by the default value of the OSTS register (for the oscillation
stabilization time, refer to 19.2 (3) Oscillation stabilization time selection register (OSTS) and CHAPTER 25
MASK OPTION/OPTION BYTE).
The status of each hardware unit during the period of reset effected by the WDTRES2 signal and after release of
the reset status is the same as when reset is effected by the RESET pin input.
For details, refer to Table 20-1 Hardware Status on RESET Pin Input.
The following figure shows the timing of the reset operation by the WDTRES2 signal.
Figure 20-6. Timing of Reset Operation by Watchdog Timer 2
f
X
f
CLK
WDTRES2 signal
(active low)
Internal system
reset signal
(active low)
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CHAPTER 20 RESET FUNCTION
Analog delay
Oscillation stabilization
time count
Overflow of oscillation stabilization time counter
User's Manual U16896EJ2V0UD
After release of the reset status, the oscillation
Initialized to f /8 operation
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