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Basic Operation
(1) Reset/external interrupt timing
= −40 to +85°C, V
(T
A
DD
Parameter
Note
RESET low-level width
NMI high-level width
NMI low-level width
INTPn high-level width
INTPn low-level width
<R>
ADTRG high-level width
<R>
ADTRG low-level width
Note The RESET low-level width is when the RESET pin input is valid (when POCRES is invalid).
Remarks 1. Nr:
Number of samplings set by the RNZC.SMPSEL bit
t
: Digital noise elimination sampling clock cycle of RESET pin
RSMP
Ni:
Number of samplings set by the NFC.NFSTS bit
t
:
Digital noise elimination sampling clock cycle of INTP3 pin
ISMP
T:
A/D base clock cycle (f
2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse
narrower than the above specification is input, therefore, it may also be detected as a valid edge.
Reset/Interrupt
RESET (input)
NMI (input)
INTPn (input)
ADTRG (input)
Remark n = 0 to 7
666
CHAPTER 28 ELECTRICAL SPECIFICATIONS
= EV
= AV
= 2.7 to 5.5 V, V
DD
REF0
Symbol
t
<87>
Reset in
WRSL1
power-on
status
t
<88>
Power-on reset
WRSL2
t
<89>
Analog noise elimination
WNIH
t
<90>
Analog noise elimination
WNIL
t
<91>
n = 0 to 7 (analog noise elimination)
WITH
n = 3 (when digital noise elimination selected)
t
<92>
n = 0 to 7 (analog noise elimination)
WITL
n = 3 (when digital noise elimination selected)
t
<93>
V
= 4.0 to 5.5 V
WADH
DD
V
= 2.7 to 5.5 V
DD
t
<94>
V
= 4.0 to 5.5 V
WADL
DD
V
= 2.7 to 5.5 V
DD
)
AD
V
DD
<88>
<89>/<91>/<93>
User's Manual U16896EJ2V0UD
= EV
= AV
= 0 V, C
SS
SS
SS
L
Conditions
When digital noise
elimination not selected
When digital noise
elimination selected
<87>
<90>/<92>/<94>
= 50 pF)
MIN.
MAX.
2
Nr × t
+ 2
RSMP
3
1
1
600
Ni × t
+ 200
ISMP
600
Ni × t
+ 200
ISMP
T + 50
T + 100
T + 50
T + 100
Unit
μ
s
μ
s
ms
μ
s
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
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