NEC V850ES/KE1+ User Manual page 196

(c) Generation timing of compare match interrupt request signal (INTTP0CC1)
The timing of generation of the INTTP0CC1 signal in the PWM output mode differs from the timing of other
INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter
matches the value of the TP0CCR1 register.
Count clock
16-bit counter
TP0CCR1 register
TOP01 pin output
INTTP0CC1 signal
Usually, the INTTP0CC1 signal is generated in synchronization with the next counting up after the count
value of the 16-bit counter matches the value of the TP0CCR1 register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed
to match the change timing of the output signal of the TOP01 pin.
196
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
− 2 − 1
D D
1 1
User's Manual U16896EJ2V0UD
D D + 1
1 1
D
1
D + 2
1