NEC V850ES/KE1+ User Manual page 451

32-bit single-chip microcontrollers
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Figure 15-4. Continuous Transfer (Receive-Only) Timing Chart
• Transmit/receive type 1, 8-bit data length
SCK0n (I/O)
SI0n (input)
SIO0nL
register
SIRBnL
register
Reg_RD
SIRBn
CSOTn bit
INTCSI0n
signal
L
SO0n (output)
rq_clr
trans_rq
<1>
<2>
Remarks 1. Reg_RD: Internal signal. This signal indicates that the SIRBnL register has been read.
rq_clr:
trans_rq: Internal signal. Transfer request signal.
2. n = 0, 1
In the case of the continuous transfer mode, two transfer requests are set at the start of the first transfer.
Following the INTCSI0n signal, transfer is continued if the SIRBnL register can be read within the next
transfer reservation period. If the SIRBnL register cannot be read, transfer ends and the SIRBnL register
does not receive the new value of the SIO0nL register.
The last data can be obtained by reading the SIO0nL register following completion of the transfer.
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0)
din-1
din-2
din-1
SIRBn (d1)
(dummy)
<3>
<4>
Period during
which next transfer
can be reserved
Internal signal. Transfer request clear signal.
User's Manual U16896EJ2V0UD
din-3
din-4
din-2
din-3
SIRBn (d2)
SIRBn (d3)
<3>
<3>
din-5
din-5
din-4
SIRBEn (d4)
SIO0n (d5)
<5>
451

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