NEC V850ES/KE1+ User Manual page 333

Operation when CMPn0 register = N, CMPn1 register = N is set
8-bit timer Hn count clock
8-bit timer 5n count clock
<R>
<R>
<1> When the TMHEn bit = 0 and the TCE5n bit = 0, the operation of 8-bit timer Hn is stopped.
<2> When the TMHEn bit is set to 1, 8-bit timer Hn starts counting. The carrier clock remains the default level.
<3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the first
INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit
timer counter Hn changes from the CMPn0 register to the CMPn1 register. 8-bit timer counter Hn is cleared
to 00H.
<4> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the INTTMHn
signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer
counter Hn changes from the CMPn1 register to the CMPn0 register. 8-bit timer counter Hn is cleared to 00H.
A carrier clock with a duty of 50% is generated through the repetition of steps <3> and <4>.
<5> The INTTM5n signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal.
<6> The INTTM5Hn signal becomes the data transfer signal of the NRZBn bit, and the value of the NRZBn bit is
transferred to the NRZn bit.
<7> The TOHn output is made low level by clearing the NRZn bit = 0.
Remark n = 0, 1
Figure 9-8. Carrier Generator Mode (1/3)
8-bit timer counter
00H
Hn count value
CMPn0
CMPn1
TMHEn
INTTMHn
<1> <2>
Carrier clock
TM5n count value
00H 01H
CR5n
TCE5n
INTTM5n
INTTM5Hn
0
NRZBn
NRZn
Carrier clock
TOHn
CHAPTER 9 8-BIT TIMER H
N 00H N 00H N 00H
N
N
<3> <4>
K 00H 01H L 00H 01H
K L
<6>
<5>
1 0
<6>
0 1
<7>
User's Manual U16896EJ2V0UD
N 00H N 00H
M 00H 01H N 00H 01H
M N
1 0
0 1
N
0
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