External Trigger Pulse Output Mode (Tp0Md2 To Tp0Md0 Bits = 010) - NEC V850ES/KE1+ User Manual

6.5.3 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010)

In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the
TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event
counter P starts counting, and outputs a PWM waveform from the TOP01 pin.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a
software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the
TOP00 pin.
Figure 6-16. Configuration in External Trigger Pulse Output Mode
Edge
TIP00 pin
detector
Software trigger
generation
Count
clock
selection
TP0CE bit
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
CCR1 buffer register
Count
start
control
CCR0 buffer register
User's Manual U16896EJ2V0UD
TP0CCR1 register
Transfer
Match signal
Clear
16-bit counter
Match signal
TP0CCR0 register
Output
S
controller TOP01 pin
R
(RS-FF)
INTTP0CC1 signal
Output
TOP00 pin
controller
INTTP0CC0 signal
Transfer
169