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CHAPTER 21 CLOCK MONITOR
Figure 21-4. Reset Timing of Clock Monitor
f
X
f
R
Oscillation stabilization time secured
f
(count operation stops)
CLK
Main clock operation stopped
f
operation
R
Program fetch
started
CLMRES signal
(active low)
Main clock stop
detected
CLME bit
CLMRF bit
WDT2 count
Count operation or count stopped
Stopped
Count operation
Count operation continues
Watchdog timer 2 count operation starts
Watchdog timer 2 overflow
(WDTRES2 does not occur)
Remark
Software cannot be used to restore the normal operation mode from the internal oscillation clock
operation mode. After reset (generation of the RESET, WDTRES2, POCRES, or LVIRES signal), the
normal operation mode can be restored only if the main clock (f
) oscillates correctly.
X
609
User's Manual U16896EJ2V0UD
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