Master Operation In Single Master System - NEC V850ES/KE1+ User Manual

16.15.1 Master operation in single master system

2
Note Release the I C0 bus (SCL0, SDA0 pins = high level) in conformity with the specifications of the product
in communication.
For example, when the EEPROM
port and output clock pulses from that output port until when the SDA0 pin is constantly high level.
Remark For the transmission and reception formats, conform to the specifications of the product in
communication.
CHAPTER 16 I
Figure 16-15. Master Operation in Single Master System
START
2 Note
Initialize I C bus
Refer to Table 4-12 Settings When Port Pins Are Used for Alternate Functions
Set ports
to set the I 2 C mode before this function is used.
IICX0 ← 0XH
Transfer clock selection
IICCL0 ← XXH
SVA0 ← XXH Local address setting
IICF0 ← 0XH
Start condition setting
Set STCEN0, IICRSV0 = 0
IICC0 ← XXH
ACKE0 = WTIM0 = SPIE0 = 1
IICE0 = 1
Yes
STCEN0 = 1?
No
Communication start preparation
SPT0 = 1
(stop condition generation)
INTIIC0
No
interrupt occurred?
Waiting for stop condition detection
Yes
Communication start preparation
STT0 = 1
(start condition generation)
Communication start
Write IIC0
(address, transfer direction specification)
INTIIC0
No
interrupt occurred?
Waiting for ACK detection
Yes
No
ACKD0 = 1?
Yes
No
TRC0 = 1?
Yes
Write IIC0
Transmission start
INTIIC0
No
interrupt occurred?
Waiting for data transmission
Yes
No
ACKD0 = 1?
Yes
No
Transfer completed?
Yes
No
Restarted?
SPT0 = 1
Yes
END
TM
outputs a low level to the SDA0 pin, set the SCL0 pin to the output
User's Manual U16896EJ2V0UD
2
C BUS
ACKE0 = 1
WTIM0 = 0
WREL0 = 1
Reception start
INTIIC0
No
interrupt occurred?
Waiting for
data reception
Yes
Read IIC0
No
Transfer completed?
Yes
ACKE0 = 0
WTIM0 = WREL0 = 1
INTIIC0
No
interrupt occurred?
Waiting for ACK detection
Yes
517