Chapter 5 Clock Generation Function; Overview - NEC V850ES/KE1+ User Manual

5.1 Overview

The following clock generation functions are available.
Main clock oscillator
<R>
<In PLL (×4) mode>
• f
= 2 to 5 MHz (f
X
• f
= 2 to 4 MHz (f
X
• f
= 2 to 2.5 MHz (f
X
<In clock through mode>
• f
= 2 to 10 MHz (f
X
Subclock oscillator
• f
= 32.768 kHz
XT
Internal oscillator
• f
= 120 to 480 kHz (240 kHz (TYP.))
R
Multiplication (×4) function by PLL (Phase Locked Loop)
• Clock-through mode/PLL mode selectable
• Usable voltage: V
Internal system clock generation
• 7 steps (f
• Operates at f
Peripheral clock generation
Clock output function
Remark f

CHAPTER 5 CLOCK GENERATION FUNCTION

= 8 to 20 MHz: 4.5 V ≤ V
XX
= 8 to 16 MHz: 4.0 V ≤ V
XX
= 8 to 10 MHz: 2.7 V ≤ V
XX
= 2 to 10 MHz: 2.7 V ≤ V
XX
= 2.7 to 5.5 V
DD
, f /2, f /4, f /8, f /16, f
XX XX XX XX XX
after the reset signal for the clock monitor is generated upon detection of main clock stop.
R
: Main clock oscillation frequency
X
f : Main clock frequency
XX
f : Subclock frequency
XT
f : Internal oscillation clock frequency
R
≤ 5.5 V)
DD
≤ 5.5 V)
DD
≤ 5.5 V)
DD
≤ 5.5 V)
DD
/32, f )
XX
XT
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