Cautions - NEC V850ES/KE1+ User Manual

3.4.8 Cautions

(1) Wait when accessing register
Be sure to set the following register before using the V850ES/KE1+.
• System wait control register (VSWC)
After setting the VSWC register, set the other registers as required.
When using an external bus, set the VSWC register and then set the various pins to the control mode by
setting the port-related registers.
(a) System wait control register (VSWC)
The VSWC register controls the bus access wait time for the on-chip peripheral I/O registers.
Access to the on-chip peripheral I/O register lasts 3 clocks (during no wait), but in the V850ES/KE1+,
waits are required according to the internal system clock frequency. Set the values shown below to the
VSWC register according to the internal system clock frequency that is used.
This register can be read or written in 8-bit units (Address: FFFFF06EH, After reset: 77H).
Operation Conditions
4.5 V ≤ V ≤ 5.5 V
DD
4.0 V ≤ V
<R>
< 4.5 V
DD
2.7 V ≤ V
<R>
< 4.0 V
DD
(b) Access to special on-chip peripheral I/O register
This product has two types of internal system buses.
One type is for the CPU bus and the other is for the peripheral bus to interface with low-speed peripheral
hardware.
Since the CPU bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access
between the CPU and peripheral hardware, illegal data may be passed unexpectedly. Therefore, when
accessing peripheral hardware that may cause a conflict, the number of access cycles is changed so that
the data is received/passed correctly in the CPU. As a result, the CPU does not shift to the next
instruction processing and enters the wait status. When this wait status occurs, the number of execution
clocks of the instruction is increased by the number of wait clocks.
Note this with caution when performing real-time processing.
When accessing a special on-chip peripheral I/O register, additional waits may be required further to the
waits set by the VSWC register.
The access conditions at that time and the method to calculate the number of waits to be inserted
(number of CPU clocks) are shown below.
Number of waits to be added = (2 + m) × k [clocks]
Number of accesses to specific on-chip peripheral I/O register = 3 + m + (2 + m) × k (clocks)
68
CHAPTER 3 CPU FUNCTIONS
Internal System Clock Frequency (f
32 kHz ≤ f
< 16.6 MHz
CLK
16.6 MHz ≤ f ≤ 20 MHz
CLK
32 kHz ≤ f ≤ 16 MHz
CPU
32 kHz ≤ f
< 8.3 MHz
CLK
8.3 MHz ≤ f ≤ 10 MHz
CLK
User's Manual U16896EJ2V0UD
) VSWC Register Setting
CLK
00H
01H
00H
00H
01H
Number of Waits
0 (no waits)
1
0 (no waits)
0 (no waits)
1