External Event Count Mode (Tp0Md2 To Tp0Md0 Bits = 001) - NEC V850ES/KE1+ User Manual

6.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001)

In the external event count mode, the valid edge of the external event count input is counted when the
TP0CTL0.TP0CE bit is set to 1, and an interrupt request signal (INTTP0CC0) is generated each time the specified
number of edges have been counted. The timer output (TOP00, TOP01 pins) cannot be used.
Usually, the TP0CCR1 register is not used in the external event count mode.
TIP00 pin
(external event
count input)
<R>
FFFFH
16-bit counter
0000H
TP0CE bit
TP0CCR0 register
INTTP0CC0 signal
Remark
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-9. Configuration in External Event Count Mode
Edge
detector
TP0CE bit
Figure 6-10. Basic Timing in External Event Count Mode
D D
0 0
D
0
External External
External
event event
event
count count
count
interval interval
interval
(D + 1) (D + 1)
(D
0 0
This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.
User's Manual U16896EJ2V0UD
Clear
16-bit counter
Match signal
CCR0 buffer register
TP0CCR0 register
D
0
16-bit counter
External event
count input
(TIP00 pin input)
TP0CCR0 register
INTTP0CC0 signal
+ 1)
0
INTTP0CC0 signal
− 1
D D 0000 0001
0 0
D
0
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