One-Shot Pulse Output Mode (Tp0Md2 To Tp0Md0 Bits = 011) - NEC V850ES/KE1+ User Manual

6.5.4 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011)

In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is
set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and
outputs a one-shot pulse from the TOP01 pin.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software
trigger is used, the TOP00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when
the counter is stopped (waiting for a trigger).
Edge
TIP00 pin
detector
Software trigger
generation
Count clock
selection
TP0CE bit
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-20. Configuration in One-Shot Pulse Output Mode
Count start
control
User's Manual U16896EJ2V0UD
TP0CCR1 register
Transfer
CCR1 buffer register
Match signal
Clear
16-bit counter
Match signal
CCR0 buffer register
Transfer
TP0CCR0 register
Output
S
controller
TOP01 pin
R
(RS-FF)
INTTP0CC1 signal
Output
S
controller TOP00 pin
R
(RS-FF)
INTTP0CC0 signal
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