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(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits are used to generate and detect various statuses.
(11) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(12) Start condition generator
This circuit generates a start condition when the IICC0.STT0 bit is set.
However, in the communication reservation disabled status (IICF0.IICRSV0 bit = 1), when the bus is not
released (IICF0.IICBSY0 bit = 1), start condition requests are ignored and the IICF0.STCF0 bit is set to 1.
(13) Stop condition generator
<R>
A stop condition is generated when the IICC0.SPT0 bit is set (1).
(14) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
IICF0.STCEN0 bit.
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CHAPTER 16 I
C BUS
User's Manual U16896EJ2V0UD
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