NEC V850ES/KE1+ User Manual page 635

Table 26-6. Wiring Between
Pin Configuration of Flash Programmer (PG-FP4)
Signal Name I/O
SI/R D Input Receive signal
X
SO/T D Output Transmit signal
X
SCK Output Transfer clock
CLK Output Clock to V850ES/KE1+
/RESET Output Reset signal
FLMD0 Input Write voltage
FLMD1 Input Write voltage
HS Input Handshake signal for
CSI00 + HS
communication
−
VDD V voltage
DD
generation/voltage
monitor
−
GND Ground
Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its
inverse signal to X2.
CHAPTER 26 FLASH MEMORY
Pin Name on
FA Board
Pin Function
SI
SO
SCK
X1
X2
/RESET
FLMD0
FLMD1
RESERVE
/HS
VDD
GND
User's Manual U16896EJ2V0UD
μ
PD70F3302, 70F3302Y and PG-FP4
With CSI00-HS With CSI00
Pin Name Pin No. Pin Name
P41/SO00 20 P41/SO00
P40/SI00 19 P40/SI00
P42/SCK00 21 P42/SCK00 21
X1 7 X1
Note Note
X2
8 X2
RESET 9 RESET
FLMD0 3 FLMD0
PDL5/ 52 PDL5/
FLMD1 FLMD1
PCM0 45 Not needed Not needed Not needed Not needed
V 4 V
DD DD
EV 33 EV
DD DD
AV 1 AV
REF0 REF0
V 6 V
SS SS
AV 2 AV
SS SS
EV 32 EV
SS SS
With UART0
Pin No. Pin Name Pin No.
20 P30/TXD0 22
19 P31/RXD0/ 23
INTP7
Not needed Not needed
7 X1 7
Note
8 X2 8
9 RESET 9
3 FLMD0 3
52 PDL5/ 52
FLMD1
4 V 4
DD
33 EV 33
DD
1 AV 1
REF0
6 V 6
SS
2 AV 2
SS
32 EV 32
SS
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