Receive Data Noise Filter - NEC V850ES/KE1+ User Manual

14.5.7 Receive data noise filter

The RXDn signal is sampled at the rising edge of the prescaler output base clock (f
value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data
not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to Figure 14-11).
Refer to 14.6.1 (1) Base clock regarding the base clock.
Also, since the circuit is configured as shown in Figure 14-10, internal processing during a receive operation is
delayed by up to 2 clocks according to the external signal status.
f
UCLK
Base clock
RXDn
Base clock
RXDn (input)
Internal signal A
Internal signal B
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART)
Figure 14-10. Noise Filter Circuit
Internal signal A
In Q
Figure 14-11. Timing of RXDn Signal Judged as Noise
Match
User's Manual U16896EJ2V0UD
In
Match detector
LD_EN
Match
Mismatch
(judged as noise)
). If the same sampling
UCLK
Internal signal B
Q
Mismatch
(judged as noise)
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