NEC V850ES/KE1+ User Manual page 198

When the TP0CE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOP00
and TOP01 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TP0CCRa
register, a compare match interrupt request signal (INTTP0CCa) is generated, and the output signal of the TOP0a pin
is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTP0OV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
The TP0CCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
that time, and compared with the count value.
Figure 6-29. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
16-bit counter
0000H
TP0CE bit
TP0CCR0 register
INTTP0CC0 signal
TOP00 pin output
TP0CCR1 register
INTTP0CC1 signal
TOP01 pin output
INTTP0OV signal
TP0OVF bit
Remark a = 0, 1
198
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
D D
00
D D
10 10
D
00
D
10
Cleared to 0 by
CLR instruction
User's Manual U16896EJ2V0UD
00
D
01
D D
11
Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
D
01
D
11 11
D
01
D
11
Cleared to 0 by
CLR instruction