NEC V850ES/KE1+ User Manual page 307

(b) Operation based on CR5n register transitions
Figure 8-6. Timing of Operation Based on CR5n Register Transitions
When the value of the CR5n register changes from N to M before the rising edge of the FFH clock
→ The value of the CR5n register is transferred at the overflow that occurs immediately after.
Count clock
TM5n count value
CR5n
TCE5n H
INTTM5n
TO5n
<1> CR5n transition (N → M)
When the value of the CR5n register changes from N to M after the rising edge of the FFH clock
→ The value of the CR5n register is transferred at the second overflow.
Count clock
TM5n count value
CR5n
TCE5n
INTTM5n
TO5n
Caution In the case of read from the CR5n register between <1> and <2>, the value that is actually
used differs (Read value: M; Actual value of CR5n register: N).
Remark n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5
t
N N + 1 N + 2
FFH 00H 01H 02H
N
<2>
t
N N + 1 N + 2
FFH 00H 01H 02H 03H
N N
H
<1> CR5n transition (N → M)
User's Manual U16896EJ2V0UD
M + 1 M + 2
M FFH 00H 01H
M
N + 1 N + 2
N FFH 00H 01H
M
<2>
M M + 1 M + 2
02H
M M + 1 M + 2
02H
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