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p. 354
Modification of Caution and addition of Caution 4 to 11.2.3 (1) Watchdog timer mode register 2 (WDTM2)
p. 355
Addition of Caution 4 to 11.2.3 (2) Watchdog timer enable register (WDTE)
p. 358
Modification of 12.2 (1) Real-time output buffer register 0 (RTBL0, RTBH0)
p. 365
Addition of Caution to 13.1 Overview
p. 369
Modification of 13.4 (1) A/D converter mode register (ADM)
p. 372
Modification of 13.4 (2) Analog input channel specification register (ADS)
p. 373
Modification of 13.4 (3) A/D conversion result register, A/D conversion result register H (ADCR,
ADCRH)
p. 375
Modification of 13.4 (4) Power fail comparison mode register (PFM)
p. 376
Modification of 13.4 (5) Power fail comparison threshold register (PFT)
p. 378
Modification of 13.5.2 Trigger modes
pp. 379, 380
Modification of 13.5.3 Operation modes
p. 385
Modification of Figure 13-7 Example of How to Reduce Power Consumption in Standby Mode
p. 387
Modification of 13.6 (9) Reading A/D conversion result register (ADCR)
p. 390
Addition of 13.6 (12) Variation of A/D conversion results, (13) A/D conversion result hysteresis
characteristics, and (14) A/D conversion operation in normal mode
p. 393
Partial addition of description to 13.7 (6) Differential linearity error
p. 400
Modification of 14.3 (2) Asynchronous serial interface status register n (ASISn)
p. 404
Addition of Caution 2 to 14.3 (6) LIN operation control register 0 (ASICL0)
p. 405
Addition of Cautions 1 to 6 to 14.3 (6) LIN operation control register 0 (ASICL0)
p. 422
Modification of 14.5.8 (2) SBF transmission
p. 422
Modification of Figure 14-14 SBF Transmission
p. 460
Modification of Figure 16-1 Block Diagram of I
p. 463
Addition of 16.2 (13) Stop condition generator
p. 464
Modification of 16.3 (1) IIC control register 0 (IICC0)
pp. 469, 470
Modification of 16.3 (2) IIC status register 0 (IICS0)
p. 473
Partial addition to 16.3 (3) IIC flag register 0 (IICF0)
p. 474
Partial addition of description to 16.3 (4) IIC clock selection register 0 (IICCL0)
p. 475
Partial addition of description to 16.3 (5) IIC function expansion register 0 (IICX0)
p. 476
Partial addition of description to 16.3 (7) IIC shift register 0 (IIC0)
p. 476
Partial addition of description to 16.3 (8) Slave address register 0 (SVA0)
p. 480
Modification of 16.5.4 ACK
p. 484
Addition of 16.5.7 Wait state cancellation method
pp. 485 to 505
Modification of 16.6 I
p. 508
Partial addition of description to 16.10 Extension Code
p. 511
Modification of 16.13.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0)
p. 511
Modification of Table 16-6 Wait Periods
p. 512
Modification of Figure 16-12 Communication Reservation Timing
p. 514
Modification of Table 16-7 Wait Periods
p. 515
Addition of (3) to (6) to 16.14 Cautions
pp. 516 to 520
Modification of 16.15 Communication Operations
p. 522
Modification of Figure 16-18 Slave Operation Flowchart (1)
APPENDIX D REVISION HISTORY
Description
2
C0
2
C Interrupt Request Signals (INTIIC0)
User's Manual U16896EJ2V0UD
(2/3)
707
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