NEC V850ES/KE1+ User Manual page 483

Master
IIC0
SCL0
Slave
IIC0
SCL0
ACKE0
Transfer lines
SCL0
SDA0
A wait state is automatically generated after a start condition is generated. Moreover, a wait state is automatically
generated depending on the setting of the IICC0.WTIM0 bit.
Normally, when the WREL0 bit is set to 1 or when FFH is written to the IIC0 register, the wait status is canceled
and the transmitting side writes data to the IIC0 register to cancel the wait status.
The master device can also cancel the wait status via either of the following methods.
• By setting the IICC0.STT0 bit to 1
• By setting the IICC0.SPT0 bit to 1
CHAPTER 16 I
Figure 16-10. Wait State (2/2)
(b) When master and slave devices both have a nine-clock wait
(master: transmission, slave: reception, and ACKE0 bit = 1)
Master and slave both wait
after output of ninth clock.
6 7 8 9
H
6 7 8 9
D2 D1 D0 ACK
Generated according to previously set ACKE0 bit value
User's Manual U16896EJ2V0UD
2
C BUS
IIC0 data write (cancel wait)
1
FFH is written to IIC0 register or
WREL0 bit is set to 1.
Wait state
Wait state
from master
from slave
and slave
1
D7
2 3
2 3
D6 D5
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