Stop Mode; Setting And Operation Status; Releasing Stop Mode - NEC V850ES/KE1+ User Manual

19.5 STOP Mode

19.5.1 Setting and operation status

The STOP mode is set when the PSMR.PSM bit is set to 1 and the PSC.STP bit is set to 1 in the normal operation
mode.
In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to
the CPU and the on-chip peripheral functions is stopped.
As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set
are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral
functions that can operate with the subclock oscillator, internal oscillator, or an external clock continue operating.
Table 19-7 shows the operation status in the STOP mode.
Because the STOP mode stops operation of the main clock oscillator, it reduces the power consumption to a level
lower than the IDLE mode. If the subclock oscillator, internal oscillator, and external clock are not used, the power
consumption can be minimized with only leakage current flowing.
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
set the STOP mode.

19.5.2 Releasing STOP mode

The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the STOP mode, or reset (except WDTRES1 signal).
After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization
time has been secured.
(1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request. If the STOP mode is set in an interrupt
servicing routine, however, an interrupt request that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, only the STOP mode is released, and that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
serviced is issued (including a non-maskable interrupt request signal), the STOP mode is released and
that interrupt request signal is acknowledged.
Table 19-6. Operation After Releasing STOP Mode by Interrupt Request Signal
Release Source
Non-maskable interrupt request signal
Maskable interrupt request signal
Caution The interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI0M, and
PSC.INTM bits to 1 becomes invalid and STOP mode is not released.
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CHAPTER 19 STANDBY FUNCTION
Interrupt Enabled (EI) Status
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is executed
User's Manual U16896EJ2V0UD
Interrupt Disabled (DI) Status
The next instruction is executed