NEC V850ES/KE1+ User Manual page 541

CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
INTC acknowledged
CPU processing
Note For the ISPR register, refer to 17.3.6 In-service priority register (ISPR).
Figure 17-4. Maskable Interrupt Servicing
INT input
Interrupt mask
released?
Yes
Priority higher than
that of interrupt currently
being serviced?
Yes
Priority higher than
that of other interrupt
requests?
Yes
Highest default
priority of interrupt requests with
the same priority?
Yes
Maskable interrupt request
PSW. NP
0
PSW. ID
0
EIPC Restored PC
EIPSW PSW
ECR. EICC Exception code
PSW. EP
0
PSW. ID
1
ISPR.
corresponding-
Note
bit
1
PC
Handler address
Interrupt servicing
User's Manual U16896EJ2V0UD
No
No
No
No
Interrupt request pending
1
1
Interrupt request pending
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