NEC V850ES/KE1+ User Manual page 697

Mnemonic Operand
SET1 bit#3,disp16[reg1] 00bbb111110RRRRR
dddddddddddddddd
reg2,[reg1] r r rr r1 11 11 1 RRRRR
0000000011100000
SHL reg1,reg2 r r rr r1 11 11 1 RRRRR
0000000011000000
imm5,reg2 r r r r r 0 1 0 1 1 0 i i i i i
SHR reg1,reg2 r r rr r1 11 11 1 RRRRR
0000000010000000
imm5,reg2 r r r r r 0 1 0 1 0 0 i i i i i
SLD.B disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d
SLD.BU disp4[ep],reg2
SLD.H disp8[ep],reg2
SLD.HU disp5[ep],reg2
SLD.W disp8[ep],reg2
SST.B reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d
SST.H reg2,disp8[ep]
SST.W reg2,disp8[ep]
ST.B reg2,disp16[reg1] r r rr r1 11 01 0 RRRRR
dddddddddddddddd
ST.H reg2,disp16[reg1]
ST.W reg2,disp16[reg1]
STSR regID,reg2 r r rr r1 11 11 1 RRRRR
0000000001000000
APPENDIX B INSTRUCTION SET LIST
Opcode
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
GR[reg2]←GR[reg2] logically shift left by GR[reg1]
GR[reg2]←GR[reg2] logically shift left
by zero-extend(imm5)
GR[reg2]←GR[reg2] logically shift right by GR[reg1]
GR[reg2]←GR[reg2] logically shift right
by zero-extend(imm5)
adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
r r r r r 0 0 0 0 1 1 0 d d d d adr←ep+zero-extend(disp4)
Note 18 GR[reg2]←zero-extend(Load-memory(adr,Byte))
r r r r r 1 0 0 0 d d d d d d d adr←ep+zero-extend(disp8)
Note 19
GR[reg2]←sign-extend(Load-memory(adr,Halfword))
r r r r r 0 0 0 0 1 1 1 d d d d adr←ep+zero-extend(disp5)
Notes 18, 20 GR[reg2]←zero-extend(Load-memory(adr,Halfword))
r r r r r 1 0 1 0 d d d d d d 0 adr←ep+zero-extend(disp8)
Note 21 GR[reg2]←Load-memory(adr,Word)
adr←ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
r r r r r 1 0 0 1 d d d d d d d adr←ep+zero-extend(disp8)
Note 19
Store-memory(adr,GR[reg2],Halfword)
r r r r r 1 0 1 0 d d d d d d 1 adr←ep+zero-extend(disp8)
Note 21 Store-memory(adr,GR[reg2],Word)
adr←GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
r r rr r1 11 01 1 RRRRR adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword)
Note 8
rrrrr111011RRRRR adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd1 Store-memory (adr,GR[reg2], Word)
Note 8
GR[reg2]←SR[regID]
User's Manual U16896EJ2V0UD
Operation
Note 3
Note 3
(5/6)
Execution Flags
Clock
i r l CY OV S Z SAT
×
3 3 3
Note 3 Note 3
×
3 3 3
Note 3 Note 3
× × ×
1 1 1 0
× × ×
1 1 1 0
× × ×
1 1 1 0
× × ×
1 1 1 0
1 1
Note 9
1 1
Note 9
1 1
Note 9
1 1
Note 9
1 1
Note 9
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
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