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(i)
Watchdog timer
Two watchdog timer channels are provided on chip to detect program loops and system abnormalities.
Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a non-
maskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs.
When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an
overflow occurs.
Watchdog timer 2 operates by default following reset release.
It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after
an overflow occurs.
(j)
Serial interface (SIO)
The V850ES/KE1+ includes three kinds of serial interfaces: an asynchronous serial interface (UARTn)
(supporting 1-channel LIN), a clocked serial interface (CSI0n), and an I
simultaneously use up to five channels.
For UARTn, data is transferred via the TXDn and RXDn pins.
For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins.
2
For I
C0, data is transferred via the SDA0 and SCL0 pins.
2
I
C0 is provided only in the
Remark n = 0, 1
(k) A/D converter
This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins.
performed using the successive approximation method.
(l)
ROM correction
This function is used to replace part of a program in the mask ROM with that contained in the internal
RAM. Up to four correction addresses can be specified.
(m) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input
pins.
(n) Real-time output function
This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare
register match signal.
A 1-channel 6-bit data real-time output function is provided on chip.
(o) Clock monitor
The clock monitor samples the main clock (f
reset request signal when the oscillation of the main clock is stopped.
(p) Low-voltage detector (LVI)
The low-voltage detector compares the supply voltage (V
an internal interrupt signal or internal reset signal when V
CHAPTER 1 INTRODUCTION
μ
PD703302Y and 70F3302Y.
) using the internal oscillation clock (f
X
User's Manual U16896EJ2V0UD
2
C bus interface (I
) and detection voltage (V
DD
< V
.
DD
LVI
2
C0), and can
Conversion is
), and generates a
R
), and generates
LVI
29
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