Table of Contents
Advertisement
FFFFH
16-bit counter
0000H
TP0CE bit
TP0CCR0 register
CCR0 buffer register
INTTP0CC0 signal
TOP00 pin output
TP0CCR1 register
CCR1 buffer register
INTTP0CC1 signal
TOP01 pin output
When the TP0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOP01 pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TP0CCR1 register) × Count clock cycle
Cycle = (Set value of TP0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TP0CCR1 register)/(Set value of TP0CCR0 register + 1)
The PWM waveform can be changed by rewriting the TP0CCRa register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts next time
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
The value set to the TP0CCRa register is transferred to the CCRa buffer register when the count value of the 16-bit
counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
Remark
a = 0, 1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-25. Basic Timing in PWM Output Mode
D
D
00
00
D
D
10
10
D
00
D
00
D
10
D
10
Active period
Cycle
(D
)
(D
+ 1)
10
00
User's Manual U16896EJ2V0UD
D
01
D
D
D
00
11
D
10
D
01
D
D
D
Inactive period
− D
(D
+ 1)
00
10
D
01
11
01
11
11
189
Advertisement
Table of Contents
