Operation - NEC V850ES/KE1+ User Manual

11.1.4 Operation

(1) Operation as watchdog timer 1
Watchdog timer 1 operation to detect a program loop is selected by setting the WDTM1.WDTM14 bit to 1.
The count clock (program loop detection time interval) of watchdog timer 1 can be selected using the
WDCS.WDCS0 to WDCS.WDCS2 bits. The count operation is started by setting the WDTM1.RUN1 bit to 1.
When, after the count operation is started, the RUN1 bit is again set to 1 within the set program loop detection
time interval, watchdog timer 1 is cleared and the count operation starts again.
If the program loop detection time is exceeded without RUN1 bit being set to 1, reset signal (WDTRES1)
through the value of the WDTM1.WDTM13 bit or a non-maskable interrupt request signal (INTWDT1) is
generated.
The count operation of watchdog timer 1 stops in the STOP mode and IDLE mode. Set the RUN1 bit to 1
before the STOP mode or IDLE mode is entered in order to clear watchdog timer 1.
Because watchdog timer 1 operates in the HALT mode, make sure that an overflow will not occur during HALT.
Cautions 1. When the subclock is selected for the CPU clock, the count operation of watchdog timer
1 is stopped (the value of watchdog timer 1 is maintained).
2. For non-maskable interrupt servicing due to the INTWDT1 signal, refer to 17.10 Cautions.
Table 11-2. Program Loop Detection Time of Watchdog Timer 1
13
2
14
2
15
2
16
2
17
2
18
2
19
2
21
2
Remark f
CHAPTER 11 WATCHDOG TIMER FUNCTIONS
Clock Program Loop Detection Time
f = 4 MHz
XW
/f 2.048 ms
XW
/f 4.096 ms
XW
/f 8.192 ms
XW
/f 16.38 ms
XW
/f 32.77 ms
XW
/f 65.54 ms
XW
/f 131.1 ms
XW
/f 524.3 ms
XW
= f : Watchdog timer 1 clock frequency
XW X
User's Manual U16896EJ2V0UD
f = 5 MHz f = 10 MHz
XW XW
1.638 ms 0.819 ms
3.277 ms 1.683 ms
6.554 ms 3.277 ms
13.11 ms 6.554 ms
26.21 ms 13.11 ms
52.43 ms 26.21 ms
104.9 ms 52.43 ms
419.4 ms 209.7 ms
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