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16.5.2 Addresses
The 7 bits of data that follow the start condition are defined as an address.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in the SVA0 register. If the address data matches the SVA0 values, the slave
device is selected and communicates with the master device until the master device generates a start condition or
stop condition.
SCL0
SDA0
INTIIC0
Note The interrupt request signal (INTIIC0) is generated if a local address or extension code is received
during slave device operation.
The slave address and the eighth bit, which specifies the transfer direction as described in 16.5.3 Transfer
direction specification below, are together written to the IIC0 register and are then output. Received addresses are
written to the IIC0 register.
The slave address is assigned to the higher 7 bits of the IIC0 register.
16.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this
transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave
device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving
data from a slave device.
SCL0
SDA0
INTIIC0
Note The interrupt request signal (INTIIC0) is generated if a local address or extension code is received
during slave device operation.
CHAPTER 16 I
Figure 16-6. Address
1
2
3
4
AD6
AD5
AD4
AD3
AD2
Address
Figure 16-7. Transfer Direction Specification
1
2
3
4
AD6
AD5
AD4
AD3
User's Manual U16896EJ2V0UD
2
C BUS
5
6
7
8
9
AD1
AD0
R/W
5
6
7
8
9
AD2
AD1
AD0
R/W
Transfer direction specification
Note
Note
479
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