Free-Running Timer Mode (Tp0Md2 To Tp0Md0 Bits = 101) - NEC V850ES/KE1+ User Manual

6.5.6 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101)

In the free-running timer mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to
1. At this time, the TP0CCRa register can be used as a compare register or a capture register, depending on the
setting of the TP0OPT0.TP0CCS0 and TP0OPT0.TP0CCS1 bits.
Internal count clock
Edge
TIP00 pin
detector
(external event
count input/
capture
Digital
trigger input)
noise
eliminator
Digital
TIP01 pin
noise
(capture
eliminator
trigger input)
Remark a = 0, 1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-28. Configuration in Free-Running Timer Mode
TP0CCR1 register
TP0CCR0 register
(compare)
Count
clock
selection
TP0CE bit
Edge
detector
TP0CCR0 register
(capture)
Edge
detector
TP0CCR1 register
User's Manual U16896EJ2V0UD
Output
controller
(compare)
Output
controller
16-bit counter
0
1
(capture)
TOP01 pin output
TOP00 pin output
TP0CCS0, TP0CCS1 bits
(capture/compare selection)
INTTP0OV signal
INTTP0CC1 signal
0
INTTP0CC0 signal
1
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