NEC V850ES/KE1+ User Manual page 256

(4) Operation in clear & start mode entered by TI010 pin valid edge input
(CR010 register: capture register, CR011 register: capture register)
Figure 7-19. Block Diagram of Clear & Start Mode Entered by TI010 Pin Valid Edge Input
(CR010 Register: Capture Register, CR011 Register: Capture Register)
Count clock
Edge
TI010 pin
detection
Edge
TI011 pin
detection
Figure 7-20. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input
(CR010 Register: Capture Register, CR011 Register: Capture Register) (1/3)
TM01 register
0000H
Operable bits
(TMC013, TMC012)
Capture & count clear input
(TI010 pin input)
Capture register
(CR010)
Capture interrupt
(INTTM010)
Capture register
(CR011)
Capture interrupt
(INTTM011)
TO01 pin output
This is an application example where the count value is captured to the CR011 register, the TM01 register is
cleared, and the TO01 pin output is inverted when the rising or falling edge of the TI010 pin is detected.
When the edge of the TI011 pin is detected, an interrupt signal (INTTM010) is generated. Mask the INTTM010
signal when it is not used.
256
CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
Operable bits
TMC013, TMC012
Capture signal
Capture
signal
(a) TOC01 = 13H, PRM01 = 30H, CRC01 = 05H, TMC01 = 0AH
L
00
0000H
L
0000H
User's Manual U16896EJ2V0UD
Clear
16-bit counter
(TM01)
Capture register
(CR011)
Capture register
(CR010)
N
M
O
P
10
L M N O P
Interrupt signal
(INTTM011)
Output
TO01 pin
controller
Interrupt signal
(INTTM010)
Q
R T
S
Q R S T