NEC V850ES/KE1+ User Manual page 460

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SDA0
Noise
eliminator
DFC0
N-ch open-drain
output
SCL0
Noise
eliminator
DFC0
N-ch open-drain
output
460
CHAPTER 16 I
Figure 16-1. Block Diagram of I
Internal bus
IIC control register 0
(IICC0)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
Slave address
Clear
register 0 (SVA0)
Set
Match
signal
SO latch
IIC shift
D Q
CL01,
register 0 (IIC0)
CL00
Data
retention time
TRC0
correction
circuit
Output control
ACK detector
Start condition
detector
Stop condition
detector
Serial clock counter
Serial clock
controller
f Prescaler
XX
CLD0 DAD0 SMC0 DFC0 CL01 CL00
User's Manual U16896EJ2V0UD
2
C BUS
2
C0
IIC status register 0 (IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
Start
condition
generator
Stop
condition
generator
ACK
generator
Wakeup controller
Interrupt request
signal generator
IICS0.MSTS0,
Serial clock EXC0, COI0
wait controller
IIC shift register 0
(IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
CLX0
IIC clock select IIC function expansion
register 0 (IICCL0) register 0 (IICX0)
Internal bus
INTIIC0
Bus status
detector
STCF0 IICBSY0 STCEN0 IICRSV0
IIC flag register 0
(IICF0)