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Figure 16-16. Master Operation in Multimaster System (3/3)
interrupt occurred?
MSTS0 = 1?
No
ACKD0 = 1?
TRC0 = 1?
WTIM0 = 1
interrupt occurred?
MSTS0 = 1?
ACKD0 = 1?
No
Transfer completed?
Restarted?
EXC0 = 1 or COI0 = 1?
Not in communication
Remarks 1. Conform the transmission and reception formats to the specifications of the product in
communication.
2. When using the V850ES/KE1+ as the master in the multimaster system, read the IICS0.MSTS0
bit for each INTIIC0 interrupt occurrence to confirm the arbitration result.
3. When using the V850ES/KE1+ as the slave in the multimaster system, confirm the status using
the IICS0 and IICF0 registers for each INTIIC0 interrupt occurrence to determine the next
processing.
520
CHAPTER 16 I
C
Communication start
Write IIC0
(address, transfer direction specification)
INTIIC0
No
Waiting for ACK detection
Yes
No
Yes
2
Yes
No
Yes
Write IIC0
Transmission start
INTIIC0
No
Waiting for data transmission
Yes
No
Yes
2
No
Yes
Yes
No
SPT0 = 1
Yes
STT0 = 1
END
C
2
Yes
No
Slave operation
1
User's Manual U16896EJ2V0UD
2
C BUS
ACKE0 = 1
WTIM0 = 0
WREL0 = 1
Reception start
INTIIC0
No
interrupt occurred?
Waiting for data
transmission
Yes
No
MSTS0 = 1?
Yes
Read IIC0
No
Transfer completed?
Yes
WTIM0 = WREL0 = 1
ACKE0 = 0
INTIIC0
No
interrupt occurred?
Waiting for ACK detection
Yes
No
MSTS0 = 1?
Yes
2
2
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