NEC V850ES/KE1+ User Manual page 162

When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
counts each time the valid edge of external event count input is detected. Additionally, the set value of the TP0CCR0
register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
cleared to 0000H, and a compare match interrupt request signal (INTTP0CC0) is generated.
The INTTP0CC0 signal is generated each time the valid edge of the external event count input has been detected
(set value of TP0CCR0 register + 1) times.
Figure 6-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMP0 control register 0 (TP0CTL0)
TP0CE
TP0CTL0 0/1
(b) TMP0 control register 1 (TP0CTL1)
TP0EST
TP0CTL1
0
(c) TMP0 I/O control register 0 (TP0IOC0)
TP0IOC0
0
(d) TMP0 I/O control register 2 (TP0IOC2)
TP0IOC2 0
162
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
0 0 0
TP0EEE
0 0 0
TP0OL1
0 0 0
TP0EES1
0 0 0
User's Manual U16896EJ2V0UD
TP0CKS2 TP0CKS1 TP0CKS0
0 0 0
TP0MD2 TP0MD1 TP0MD0
0 0 0
TP0OE1 TP0OL0 TP0OE0
0 0 0
TP0EES0 TP0ETS1 TP0ETS0
0/1 0/1 0
0
0: Stop counting
1: Enable counting
1
0, 0, 1:
External event count mode
0
0: Disable TOP00 pin output
0: Disable TOP01 pin output
0
Select valid edge
of external event
count input