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4.6 Cautions
4.6.1 Cautions on bit manipulation instruction for port n register (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value
of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
When PDL0 is an output port, PDL1 to PDL7 are input ports (all pin statuses are high level), and the
value of the port latch is 00H, if the output of output port PDL0 is changed from low level to high
level via a bit manipulation instruction, the value of the port latch is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is
1 are the output latch and pin status, respectively.
A bit manipulation instruction is executed in the following order in the V850ES/KE1+.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the value of the output latch (0) of PDL0, which is an output port, is read, while the pin
statuses of PDL1 to PDL7, which are input ports, are read. If the pin statuses of PDL1 to PDL7 are
high level at this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
PDL0
PDL1 to PDL7
Port DL latch
0
0
0
0
CHAPTER 4 PORT FUNCTIONS
Figure 4-21. Bit Manipulation Instruction (PDL0)
Bit manipulation
instruction
(set1 0, PDL[r0])
Low-level output
is executed for
PDL0 bit.
Pin status: High level
0
0
0
0
Bit manipulation instruction for PDL0 bit
<1> The PDL register is read in 8-bit units.
•
In the case of PDL0, an output port, the value of the port latch (0) is read.
•
In the case of PDL1 to PDL7, input ports, the pin status (1) is read.
<2> Set PDL0 bit to 1.
<3> Write the results of <2> to the output latch of the PDL register in 8-bit units.
User's Manual U16896EJ2V0UD
PDL0
PDL1 to PDL7
Port DL latch
1
1
1
1
1
Low-level output
Pin status: High level
1
1
1
123
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