Cpu Register Set - NEC V850ES/KE1+ User Manual

3.2 CPU Register Set

The CPU registers of the V850ES/KE1+ can be classified into two categories: a general-purpose program register
set and a dedicated system register set. All the registers have 32-bit width.
For details, refer to the V850ES Architecture User's Manual.
(1) Program register set
31
r0 (Zero register)
r1 (Assembler-reserved register)
r2
r3 (Stack pointer (SP))
r4 (Global pointer (GP))
r5 (Text pointer (TP))
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30 (Element pointer (EP))
r31 (Link pointer (LP))
31
PC (Program counter)
CHAPTER 3 CPU FUNCTIONS
0 31
EIPC
EIPSW
FEPC
FEPSW
ECR
PSW
CTPC
CTPSW
DBPC
DBPSW
CTBP
0
User's Manual U16896EJ2V0UD
(2) System register set
(Interrupt status saving register)
(Interrupt status saving register)
(NMI status saving register)
(NMI status saving register)
(Interrupt source register)
(Program status word)
(CALLT execution status saving register)
(CALLT execution status saving register)
(Exception/debug trap status saving register)
(Exception/debug trap status saving register)
(CALLT base pointer)
0
41