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19.3 HALT Mode
19.3.1 Setting and operation status
The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply
to the other on-chip peripheral functions continues.
As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was
set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating.
Table 19-3 shows the operation status in the HALT mode.
The average power consumption of the system can be reduced by using the HALT mode in combination with the
normal operation mode for intermittent operation.
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
2. If the HALT instruction is executed with an unmasked interrupt request signal held pending,
the system shifts to the HALT mode, but the HALT mode is immediately released by the
pending interrupt request signal.
19.3.2 Releasing HALT mode
The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT1, INTWDT2
signal), an unmasked maskable interrupt request signal, and reset signal (RESET pin input, WDTRES1, WDTRES2,
POCRES, LVIRES, CLMRES signal).
After the HALT mode has been released, the normal operation mode is restored.
(1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request. If the HALT mode is set in an interrupt
servicing routine, however, an interrupt request that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, only the HALT mode is released, and that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
serviced is issued (including a non-maskable interrupt request signal), the HALT mode is released and
that interrupt request signal is acknowledged.
Table 19-2. Operation After Releasing HALT Mode by Interrupt Request Signal
Release Source
Non-maskable interrupt request signal
Maskable interrupt request signal
(2) Releasing HALT mode by reset
The same operation as the normal reset operation is performed.
578
CHAPTER 19 STANDBY FUNCTION
Interrupt Enabled (EI) Status
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is
executed
User's Manual U16896EJ2V0UD
Interrupt Disabled (DI) Status
The next instruction is executed
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