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Figure 7-16. Timing Example of Clear & Start Mode Entered by TI010 Pin Valid Edge Input
(CR010 Register: Compare Register, CR011 Register: Capture Register) (2/2)
(b) TOC01 = 13H, PRM01 = 10H, CRC01 = 04H, TMC01 = 0AH, CR010 = 0003H
TM01 register
0003H
0000H
Operable bits
(TMC013, TMC012)
Capture & count clear input
(TI010 pin input)
Compare register
(CR010)
Compare match interrupt
(INTTM010)
Capture register
(CR011)
Capture interrupt
(INTTM011)
TO01 pin output
This is an application example where the width set to the CR010 register (4 clocks in this example) is to be
output from the TO01 pin when the count value has been captured & cleared.
The count value is captured to the CR011 register, a capture interrupt signal (INTTM011) is generated, the
TM01 register is cleared (to 0000H), and the output level of the TO01 pin is inverted when the valid edge of the
TI010 pin is detected. When the count value of the TM01 register is 0003H (four clocks have been counted), a
compare match interrupt signal (INTTM010) is generated and the output level of the TO01 pin is inverted.
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
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0003H
0000H
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User's Manual U16896EJ2V0UD
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S
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