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FFFFH
16-bit counter
0000H
TP0CE bit
External trigger input
(TIP00 pin input)
TP0CCR0 register
INTTP0CC0 signal
TOP00 pin output
<R>
(software trigger)
TP0CCR1 register
INTTP0CC1 signal
TOP01 pin output
16-bit timer/event counter P waits for a trigger when the TP0CE bit is set to 1. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOP01 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOP00 pin is inverted. The TOP01 pin outputs a high level regardless of the status
<R>
(high/low) when a trigger occurs.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TP0CCR1 register) × Count clock cycle
Cycle = (Set value of TP0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TP0CCR1 register)/(Set value of TP0CCR0 register + 1)
The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts next time
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
The value set to the TP0CCRa register is transferred to the CCRa buffer register when the count value of the 16-bit
counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input signal, or setting the software trigger (TP0CTL1.TP0EST bit) to 1 is used
as the trigger.
Remark
a = 0, 1
170
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-17. Basic Timing in External Trigger Pulse Output Mode
D
0
D
1
Wait
Active level
for
width (D
)
1
trigger
Cycle (D
+ 1)
0
User's Manual U16896EJ2V0UD
D
0
D
D
1
D
0
D
1
Active level
width (D
)
1
Cycle (D
+ 1)
0
D
D
0
0
D
1
1
Active level
width (D
)
1
Cycle (D
+ 1)
0
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