Eliminating Noise On Capture Trigger Input Pin (Tip0A) - NEC V850ES/KE1+ User Manual

6.6 Eliminating Noise on Capture Trigger Input Pin (TIP0a)

The TIP0a pin has a digital noise eliminator.
However, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is
used as an external event count input pin or external trigger input pin.
Digital noise can be eliminated by specifying the alternate function of the TIP0a pin using the PMC3, PFC3, and
PFCE3 registers.
The number of times of sampling can be selected from three or two by using the PaNFC.PaNFSTS bit. The
sampling clock can be selected from f
PaNFC.PaNFC0 bits.
(1) TIP0a noise elimination control register (PaNFC)
This register is used to select the sampling clock and the number of times of sampling for eliminating digital
noise.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
PaNFC
(a = 0, 1)
PaNFSTS
PaNFC2
Cautions 1. Enable starting the 16-bit counter of TMP0 (TP0CTL.TP0CE bit = 1) after the lapse of the
sampling clock period × number of times of sampling.
2. Be sure to clear bits 7, 5 to 3 to "0".
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
, f /2, f /4, f
XX XX XX
R/W Address: P0NFC FFFFFB00H, P1NFC FFFFFB04H
0 PaNFSTS 0
Setting of number of times of sampling for eliminating digital noise
0 Number of times of sampling = 3
1 Number of times of sampling = 2
PaNFC1 PaNFC0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
Other than above
User's Manual U16896EJ2V0UD
/16, f /32, or f /64, by using the PaNFC.PaNFC2 to
XX XX XX
0 0 PaNFC2 PaNFC1 PaNFC0
Sampling clock selection
f
XX
f /2
XX
f /4
XX
f /16
XX
f /32
XX
f /64
XX
Setting prohibited
221