Periods In Which Interrupts Are Not Acknowledged By Cpu; Cautions - NEC V850ES/KE1+ User Manual

17.9 Periods in Which Interrupts Are Not Acknowledged by CPU

Interrupts are acknowledged by the CPU while an instruction is being executed.
acknowledged between an interrupt request non-sample instruction and the next instruction (interrupts are held
pending).
The following instructions are interrupt request non-sample instructions.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instructions (vs. PSW)
• Store instruction for the PRCMD register
• Store instruction and SET1, NOT1, and CLR1 instructions for the following registers
• Interrupt-related registers:
Interrupt control register (xxlCn), interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3)
• Power save control register (PSC)

17.10 Cautions

Design the system so that restoring by the RETI instruction is as follows after a non-maskable interrupt triggered by
a non-maskable interrupt request signal (INTWDT1/INTWDT2) is serviced.
<R>
<R>
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 17-15. Restoring by RETI Instruction
Generation of INTWDT1/INTWDT2
FEPC ← software reset processing address
FEPSW ← value so that NP bit = 1, EP bit = 0
↓
RETI
Ten RETI instructions (FEPC and FEPSW
↓
PSW ← initial set value of PSW
↓
Initialization processing
Note FEPSW ← value to set NP bit = 1, EP bit = 0
INTWDT1/INTWDT2 servicing routine
Note
must be set)
Software reset processing routine
User's Manual U16896EJ2V0UD
However, no interrupt is
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