NEC V850ES/KE1+ User Manual page 199

When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is
detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and a capture interrupt request
signal (INTTP0CCa) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTP0OV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
Figure 6-30. Basic Timing in Free-Running Timer Mode (Capture Function)
FFFFH
16-bit counter
0000H
TP0CE bit
TIP00 pin input
TP0CCR0 register
INTTP0CC0 signal
TIP01 pin input
TP0CCR1 register
INTTP0CC1 signal
INTTP0OV signal
TP0OVF bit
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
D
10
D
00
D
Cleared to 0 by
CLR instruction
User's Manual U16896EJ2V0UD
D
11
D
12
D
01
D
02
D D
00 01
D D
10 11
Cleared to 0 by Cleared to 0 by
CLR instruction CLR instruction
D
13
D
03
D
02 03
D D
12 13
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