Continuous Transmission Operation - NEC V850ES/KE1+ User Manual

32-bit single-chip microcontrollers
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14.5.3 Continuous transmission operation

UARTn can write the next transmit data to the TXBn register at the timing that the transmit shift register starts the
shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even
during the transmission completion interrupt service after the transmission of one data frame. In addition, reading the
ASIFn.TXSFn bit after the occurrence of a transmission completion interrupt request signal (INTSTn) enables the
TXBn register to be efficiently written twice (2 bytes) without waiting for the transmission of 1 data frame.
When continuous transmission is performed, data should be written after referencing the ASIFn register to confirm
the transmission status and whether or not data can be written to the TXBn register.
Caution The values of the ASIF.TXBFn and ASIF.TXSFn bits change 10 → 11 → 01 in continuous
transmission.
Therefore, do not confirm the status based on the combination of the TXBFn and TXSFn bits.
Read only the TXBFn bit during continuous transmission.
TXBFn
0
Writing is enabled
1
Writing is not enabled
Caution When transmission is performed continuously, write the first transmit data (first byte) to the
TXBn register and confirm that the TXBFn bit is 0, and then write the next transmit data (second
byte) to the TXBn register. If writing to the TXBn register is performed when the TXBFn bit is 1,
transmit data cannot be guaranteed.
The communication status can be confirmed by referring to the TXSFn bit.
TXSFn
0
Transmission is completed.
1
Under transmission.
Cautions 1. When initializing the transmission unit when continuous transmission is completed, confirm
that the TXSFn bit is 0 after the occurrence of the transmission completion interrupt, and
then execute initialization. If initialization is performed when the TXSFn bit is 1, transmit data
cannot be guaranteed.
2. While transmission is being performed continuously, an overrun error may occur if the next
transmission is completed before the INTSTn interrupt servicing following the transmission
of 1 data frame is executed. An overrun error can be detected by embedding a program that
can count the number of transmit data and referencing the TXSFn bit.
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART)
Whether or Not Writing to TXBn Register Is Enabled
Transmission Status
User's Manual U16896EJ2V0UD
411

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