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19.7 Sub-IDLE Mode
19.7.1 Setting and operation status
The sub-IDLE mode is set when the PSMR.PSM bit is cleared to 0 and the PSC.STP bit is set to 1 in the subclock
operation mode.
In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral
functions is stopped.
As a result, program execution is stopped and the contents of the internal RAM before the sub-IDLE mode was set
are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral
functions that can operate with the subclock, internal oscillator, or an external clock continue operating.
Table 19-10 shows the operation status in the sub-IDLE mode.
Because the sub-IDLE mode stops operation of the CPU and other on-chip peripheral functions, it can reduce the
power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has
been stopped, the power consumption can be reduced to a level as low as that in the STOP mode.
Caution Following the store instruction to set the PSC register to the sub-IDLE mode, insert five or more
<R>
NOP instructions.
19.7.2 Releasing sub-IDLE mode
The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the sub-IDLE mode, or reset (except WDTRES1 signal).
When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set. If it is
released by reset, the normal operation mode is restored.
(1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable
interrupt request signal, regardless of the priority of the interrupt request. If the sub-IDLE mode is set in an
interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, only the sub-IDLE mode is released, and that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
serviced is issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and
that interrupt request signal is acknowledged.
Release Source
Non-maskable interrupt request signal
Maskable interrupt request signal
Caution The interrupt request signal that is disabled by setting the PSC.NMI2M, PSC.NMI0M, and
PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not released.
CHAPTER 19 STANDBY FUNCTION
Table 19-9. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is
executed
Interrupt Enabled (EI) Status
User's Manual U16896EJ2V0UD
Interrupt Disabled (DI) Status
The next instruction is executed
587
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